library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SF_ODLFifo_XmtInterface_Xmt0to3 is
  port( 							
    clk, reset: in std_logic;
		
		--length FIFO signals
	lfifo_wreq:  in std_logic;
	lfifo_full: out std_logic;
	lfifo_input: in std_logic_vector(11 downto 0);--, lfifo_output: std_logic_vector(11 downto 0);

	--data FIFO signals
	dfifo_wreq: in std_logic;
	dfifo_full: out std_logic;
	dfifo_input: in std_logic_vector(7 downto 0);
	
	--output port number FIFO signals
	pfifo_wreq: in std_logic; 
	pfifo_full: out std_logic;
	pfifo_input: in std_logic_vector(3 downto 0);

	--inputs from xmt to SF_fifo2xmt_interface
	xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: in std_logic_vector(12 downto 0);

	--outputs to xmt from SF_fifo2xmt_interface
	o_D_xmt: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
	o_L_xmt: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
	xmt_dwtreq, xmt_lwtreq: out std_logic_vector (3 downto 0); --read/write request to xmt data and length FIFOs	
--	count_test: out std_logic_vector (11 downto 0); -- test pins to be comented out after simulations

--  Test pins
    ODL_emp: out std_logic_vector (2 downto 0)
--	w_testL, w_testD: out std_logic_vector(3 downto 0)
	);

end SF_ODLFifo_XmtInterface_Xmt0to3;

Architecture arch of SF_ODLFifo_XmtInterface_Xmt0to3 is 

------------Signals
		
	--input to SF_fifo2xmt_interface from FIFOs (jacob)
	signal s_ODL_emp: std_logic_vector  (2 downto 0);	   -- monitors SF FIFOs  --s_o_D_xmt
	signal s_i_D_FIFO: std_logic_vector (7 downto 0);     -- input from 8 bit Data FIFO  
	signal s_i_L_FIFO: std_logic_vector (11 downto 0);    -- input from 12 bit Length FIFO, s_o_L_xmt
	signal s_i_O_FIFO: std_logic_vector (3 downto 0);     -- input from 3(now 4) bit Output Port FIFO
	--output from SF_fifo2xmt_interface (jacob)
	signal s_rd_D_FIFO, s_rd_L_FIFO, s_rd_O_FIFO: std_logic;	--read requests for Data, Length, and output FIFOs	
	signal s_xmt_dwtreq, s_xmt_lwtreq: std_logic_vector (3 downto 0);
	--inputs from xmt to SF_fifo2xmt_interface
--	signal xmt0_wused,	xmt1_wused,	xmt2_wused,	xmt3_wused: std_logic_vector(11 downto 0);


	component SF_fifo2xmt_interface is  --(jacob)
	port(
	reset, clk: in std_logic;
	ODL_emp: in std_logic_vector (2 downto 0);	    -- monitors SF FIFOs
	i_D_FIFO: in std_logic_vector (7 downto 0);     -- input from 8 bit Data FIFO
	i_L_FIFO: in std_logic_vector (11 downto 0);    -- input from 12 bit Length FIFO
	i_O_FIFO: in std_logic_vector (3 downto 0);     -- input from 3 (now 4 bit) bit Output Port FIFO
	rd_D_FIFO, rd_L_FIFO, rd_O_FIFO: out std_logic;	-- read requests for Data, 
													-- Length, and output FIFOs
	o_D_xmt: out std_logic_vector (7 downto 0);     -- out to xmt D FIFOs
	o_L_xmt: out std_logic_vector (11 downto 0);    -- out to xmt L FIFOs
		--pins for testing internal coutner
--	count_test: out std_logic_vector (11 downto 0); 
		--control path inputs from xmt port
	xmt_wordsused0, xmt_wordsused1: in std_logic_vector (12 downto 0);
	xmt_wordsused2, xmt_wordsused3: in std_logic_vector (12 downto 0);
		--data path outputs to xmt port
	xmt_dwtreq, xmt_lwtreq: out std_logic_vector (3 downto 0)
    );
    end component;
 
		
	--Switch Fabric FIFOs
	component Output_FIFO IS
	PORT(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);    --changed to four bit FIFO
		usedw		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
	end component;
	
	component FIFO_Data_Length IS  --this is the FIFO holding the packet length value (jacob)
	PORT (
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
	);
	end component;
		
	component Data_FIFO IS  --this is the data packet FIFO
	PORT(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		empty		: OUT STD_LOGIC ;
		full		: OUT STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
	);
	end component;
	
begin

		
	fifo2xmt_interface : SF_fifo2xmt_interface --(jacob)
	port map (
	reset => reset,
	clk => clk,
	ODL_emp 	=> 	s_ODL_emp,
	i_D_FIFO 	=> 	s_i_D_FIFO,--in to
	i_L_FIFO 	=> 	s_i_L_FIFO, 
	i_O_FIFO 	=> 	s_i_O_FIFO,
	rd_D_FIFO 	=> 	s_rd_D_FIFO, 
	rd_L_FIFO 	=> 	s_rd_L_FIFO, 
	rd_O_FIFO 	=> 	s_rd_O_FIFO,
	o_D_xmt 	=> 	o_D_xmt, --s_o_D_xmt,	--directly connected to data bus going to xmt
	o_L_xmt 	=> 	o_L_xmt,		--directly connected to length bus going to xmt
		--pins for testing internal coutner
--	count_test => count_test,
		--control path inputs from xmt port
	xmt_wordsused0 	=> xmt0_wused,
	xmt_wordsused1 	=> xmt1_wused,
	xmt_wordsused2 	=> xmt2_wused,
	xmt_wordsused3 	=> xmt3_wused,
		--data path outputs to xmt port
	xmt_dwtreq 		=> xmt_dwtreq,
	xmt_lwtreq 		=> xmt_lwtreq
    );



	--Switch Fabric Internal FIFOs
	pfifo: Output_FIFO PORT MAP (
		aclr 	=> 	reset,
		clock 	=> 	clk,
		data 	=>  pfifo_input,    -- from SF table (wwz)
		rdreq	=> 	s_rd_O_FIFO, 
		wrreq 	=> 	pfifo_wreq,    -- from SF table (wwz)
		empty 	=> 	s_ODL_emp(0),
		full 	=> 	pfifo_full, --monitor for SF table (wwz)
		q 		=>	s_i_O_FIFO,
		usedw => open
	);

	L_FIFO : FIFO_Data_Length  --this is the FIFO Holding the Packet Length (jacob & xuan)
	Port Map
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> lfifo_input,	   	--in from Rcv side (xuan)
		rdreq 	=> s_rd_L_FIFO,
		wrreq	=> lfifo_wreq,	   	--in from Rcv side  (xuan)
		empty 	=> s_ODL_emp(2),     --lfifo_empty, 	--
		full 	=> lfifo_full,
		q 		=> s_i_L_FIFO,
		usedw 	=> open
	);	
	
	D_FIFO : Data_FIFO  --this is the FIFO Holding the Data (jacob & xuan)
	PORT MAP
	(
		aclr 	=> reset,
		clock 	=> clk,
		data	=> dfifo_input, 	--in from rcvr (xuan)
		rdreq 	=> s_rd_D_FIFO,
		wrreq	=> dfifo_wreq,			-- in from rcvr (xuan)
		empty 	=> s_ODL_emp(1),
		full 	=> dfifo_full,
		q 		=> s_i_D_FIFO,
		usedw 	=> open
	);

ODL_emp <= s_ODL_emp;
--w_testL <= s_snd_L;
--w_testD <= s_snd_L;
end arch;